Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device including a one-side-contact, and a method for fabricating the semiconductor device.
As miniaturization of semiconductor devices continues and 30 nm or 20 nm process are being developed, conventional technologies are reaching their limits. To overcome such difficulty, further increases in die utilization with processes under 4F2 is being sought by using a vertical gate (VG) and buried bit line (BBL).
FIG. 1 is a cross-sectional view of a conventional semiconductor device. Referring to FIG. 1, a plurality of pillar structures each include an active pillar 12, a hard mask layer 13 extended perpendicularly to a substrate 11, a gate insulation layer 14 and a vertical gate 15 surrounding the external walls of the active pillar 12. The substrate 11 includes buried bit lines 16 formed therein by performing an ion implantation process with an impurity. Neighboring buried bit lines 16 are separated from one another by trenches 17, and the trenches 17 are filled with an interlayer dielectric layer 18.
According to the prior art shown in FIG. 1, the buried bit lines 16 each buried at the lower portion of the vertical gate 15 are formed by implanting a dopant through an ion implantation process.
However, the buried bit lines 16 formed using such a conventional technology have a high resistance and thus the operation speed may decrease. Also, the conventional technology requires the formation of the trenches 17 for separating neighboring buried bit lines 16 from one another so that cells become larger in order to accommodate the trench formation. However, such an increase in cell sizes is less desirable for high integration.